paolo lazzaroni

Diffraction-limited storage rings are posing huge challenges on the detectors required in new generation x-ray experiments, especially those based on continuous-wave operation. A modern mixed-signal readout channel demands strict requirements on noise, power consumption, and frame rate, asking for advancements in both analog and digital design. The proposed readout channel, pFREYA, is designed for pixellated detectors to be employed in continuous-wave x-ray science applications (e.g., ptychography) with a frame rate of 1 MHz. It is developed in a commercial 65nm CMOS technology and features single photon resolution at 5 keV, 9 keV, 18 keV, and 25 keV photon energies, a power consumption of 220 μW, and a pixel area of 150μm\texttimes 150 μm. It also offers a 2-bit switchable peaking time selection for signal-to-noise ratio optimisation, signal-over-threshold identification for zero-suppression, and 10-bit analogto- digital conversion per channel. In the present work an overview on the readout channel architecture will be given and results from the characterisation of the CSA and the shaper employed in the architecture will be provided, in addition to the noise performance of the pFREYA channel.

The General Anti Particle Spectrometer (GAPS) is a balloon-borne cosmic-ray experiment which is currently in its last phase of construction, undergoing system testing, and scheduled for a long-duration balloon flight from McMurdo Station in the Antarctic in December 2024. Its primary scientific goal is the search for light antinuclei in cosmic rays at kinetic energies below 0.25 GeV/\n\. This energy region is especially of interest for beyond-the-standard model dark matter searches and is still mostly uncharted. Searches for light antimatter nuclei with energies below ~0.25 GeV/\n are a novel approach to the search for dark matter because wide range of dark matter models proposes annihilation or decay into matter-antimatter pairs. GAPS will yield unprecedented sensitivity to low-energy antideuterons and will measure the low-energy antiproton spectrum with high statistics and precision. To reach the required sensitivity, the GAPS detector incorporates a new approach for antimatter detection, utilizing a tracker with custom, lithium-drifted silicon detectors, designed to measure the X-ray cascade expected from antimatter capture and charged particles from the subsequent annihilation. It also utilizes a fast time-of-flight system, allowing for a high-precision beta measurement. This proceeding highlights GAPS scientific goals.

This paper reports the design and experimental results from the characterization of an integrated circuit developed for the readout of the X-ray spectrometer and tracking system of the General AntiParticle Spectrometer (GAPS) balloon mission. GAPS will search for an indirect signature of dark matter through the detection of low-energy (<0.25 GeV/n) cosmic-ray antiprotons, antideuterons and antihelium nuclei. The ASIC, named SLIDER32 (32 channels Si-LI DEtector Readout ASIC), was fabricated in a 180 nm CMOS technology and is comprised of 32 analog readout channels, an 11-bit SAR ADC and a digital back-end section which is responsible for defining channel settings and for sending digital information to the data acquisition system. The core of the ASIC is a low-noise analog channel implementing a dynamic signal compression which makes the chip suitable for resolving both X-rays in the range of 20 to 100 keV and charged particles with energy deposition of up to 100 MeV. It features an energy resolution of 4 keV FWHM in the 20–100 keV range with a 40 pF detector capacitance, to clearly distinguish X-rays from antiprotonic or antideuteronic exotic atoms. The readout electronics of the ASIC will run at a temperature of about –40 ^∘C, complying with a detector leakage current of the order of 5–10 nA per strip.

This work reports the current state of the development of a pixelated readout for nanometer resolution X-ray ptychography applications. A very dense, low-noise and low-power pixel developed in a commercial 65nm CMOS technology is envisioned for such applications, targeting a pixel area of 150 μm \texttimes 150 μm, an overall noise of 200e- rms and a power consumption of 150μW per pixel. In the paper, an introduction to the application and an overview of the experimental setup are given, the designed frontend channel is reported and revised in its components and simulation results of the schematic-level design are shown and discussed.